1. Field of the Invention
The present invention relates to a digital-to-analog converter for converting an input digital signal into an analog signal, and an image display device having the converter for each signal line for driving a pixel portion.
2. Description of the Related Art
FIG. 1 shows a basic structure of a resistor string type D/A converter.
A resistor string RS including a series connection body of a plurality of N resistor elements RE0, RE1, . . . , RE(2N−2), and RE(2N−1) is connected between an input terminal Tb for a minimum voltage (analog lower limit value) Vb of an analog voltage to be outputted and an input terminal Tt for a maximum voltage (analog upper limit value) Vt of the analog voltage.
Switches are connected to nodes between the resistor elements and a connection node between a resistor element at an end and the input terminal Tb or the input terminal Tt (a connection node on the input terminal Tt side in this case), respectively. In the example of FIG. 1, a switch S0 is connected to the connection node between the resistor elements RE0 and RE1. Likewise, a switch S1 is connected to the connection node between the resistor elements RE1 and RE2. This connection relationship is repeated for other switches S3 to S(2N−1) while the resistor elements are shifted one by one.
The N switches S0 to S(2N−1) are short-circuited on a side opposite from the resistor elements and are connected to an output terminal To.
When the D/A converter selects one switch according to a digital signal of N bits inputted to the D/A converter, a desired analog D.C. voltage resulting from equally dividing (Vt−Vb) by 2N is obtained as an output voltage Vo from the output terminal To.
When the number of bits is N, the number of necessary analog switches (switches) is 2N in the D/A converter of this configuration. Thus, the D/A converter of this configuration is disadvantageous in that in the case of conversion of multiple bits, the number of switches becomes enormous.
A D/A converter having a configuration of a plurality of stages in which converter the number of switches can be reduced is known (see Patent Document 1, for example).
Patent Document 1 discloses a two-stage configuration including a first-stage D/A converter for converting m higher order bits and a next-stage D/A converter for converting n lower order bits. The first-stage D/A converter is of a resistor string type. Two examples of switch connection configuration of the first-stage D/A converter are disclosed. The switch connection configurations will be described below.
FIG. 2A is a circuit diagram of a higher order D/A converter. Incidentally, in this diagram, the order in which numbers of resistor elements RE and switches are arranged is the reverse of that of FIG. 1.
The D/A converter shown in FIG. 2A has two switches Sit and Sib (i=1, 2, 3, 4, . . . ) connected in parallel with each other to a node between resistor elements RE in a resistor string RS similar to that of FIG. 1. Outputs of a switch Sit group including half of the switches are connected to a common output terminal Tot. Outputs of a switch Sib group including the other half of the switches are connected to a common output terminal Tob.
FIG. 2B shows correspondences between switches selected and turned on in a pair and input bits in a case where the number of input bits is four. As indicated by the correspondences, two switches are always selected as switches at both ends of a resistor element RE. Hence, voltages Vtt and Vbb at both ends of one resistor element REi (i=1, 2, 3, 4, . . . ) identified by a code of higher order bits of an input digital signal are outputted from the two output terminals Tot and Tob. While the values of the voltages Vtt and Vbb differ depending on which resistor element RE is selected, the voltages Vtt and Vbb have a fixed voltage difference and serve as reference voltages for the lower order D/A converter.
For example, when the switches S3t and S4b are selected and turned on, voltages at both ends of the resistance RE3 are supplied to the lower order D/A converter.
When the lower order D/A converter is of a resistor string type, the two selected voltages are applied to both ends of a lower order resistor string RS, and lower order D/A conversion is similarly performed. This lower order D/A converter is realized with the same configuration as in FIG. 1 to provide one analog output. Incidentally, in Patent Document 1, the lower order D/A converter is of an R-2R ladder resistor type.
When the configuration shown in FIG. 2A is used for N higher order bits, and the configuration shown in FIG. 1 is used for M lower order bits, the total number of switches is a number obtained by adding the number of higher order switches (2×2N−2) to the number of lower order switches (2M).
The total number of switches in FIG. 2A is reduced as compared with the number of switches at the time of the one-stage configuration in FIG. 1, that is, 2(N+M), but a switch reduction rate is low because two switches are connected to a node between resistor elements RE.
A configuration in which the number of switches is further reduced is disclosed in Patent Document 1.
FIG. 3A is a circuit diagram of a higher order D/A converter of this configuration.
While two switches are connected to a node between resistor elements RE in FIG. 2A, one switch is connected to a node between resistor elements RE in FIG. 3A. Thus the number of switches is halved. Switches S0t, S1b, S2t, S3b, . . . are alternately connected to output terminals Tot and Tob.
FIG. 3B shows correspondences between switches selected and turned on in a pair and input bits in a case where the number of input bits is four.
As indicated by the correspondences, as in the case of FIG. 2B, two switches are always selected as switches at both ends of a resistor element RE. In this case, however, identical switches are each selected twice.
In the D/A converter illustrated in FIG. 3A, the number of switches can be further reduced as compared with the D/A converter illustrated in FIG. 2A.
[Patent Document 1]
Japanese Patent Laid-Open No. 2003-224477 (description of related art, FIG. 10, FIG. 11, FIG. 13 and the like)